Monolithic ICs generally comprise a number of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated over a planar substrate, such as a silicon wafer. System-on-a-chip (SoC) architectures utilize transistors in both analog and digital circuitry. Monolithic integration of high-speed analog and digital circuitry can be problematic, in part, because digital switching can induce substrate noise that can limit precision and linearity of analog circuitry. Greater substrate isolation is therefore advantageous for improved SoC performance.
FIG. 1A illustrates an arrangement of a monolithic device structure 101 that may be employed to measure substrate isolation between a first port (Port 1) and a second port (Port 2). Generally, a signal S1 is applied to Port 1 and strength of a corresponding noise signal S2 is measured at Port 2 with isolation defined as the ratio of the two signal strengths (S2/S1). Guard ring structures, such as guard ring 110, and well isolation structures, such as deep well 120, may be provided to improve substrate isolation. As shown, guard ring 110 forms P/N/P impurity type regions ensuring a reversed diode surrounds any noise sensitive circuitry (e.g., one or more transistors of analog circuitry). Such guard ring structures may improve isolation by 20 dB, or more. Substrate isolation can be further improved with the exemplary deep well 120, which includes an n-type region disposed below a p-well (e.g., in which n-type transistors might be disposed) within guard ring 110. The n-type regions of guard ring 110 and deep well 120 may be made continuous, as often found in a triple-well process, to further improve substrate isolation between Ports 1 and 2. Such deep well isolations may improve isolation by 35 dB, or more, relative to a guard ring structure alone.
Deep well structures are typically fabricated through ion implantation, for example with a high-energy phosphorus implant for an n-well. High energy is required to achieve sufficient well depth, which may be hundreds of nanometers below a top surface of the substrate, particularly where the overlying active device silicon has a non-planar (e.g., finFET) architecture 102, as depicted in FIG. 1B. Such implant processes however can damage overlying active device silicon 150 and are also associated with implanted species concentration profiles that can be a limiter of device scaling.
Device structures and techniques for well doping which offer good isolation and are amenable to non-planar device architectures would therefore be advantageous.